The maximal ideal density of a 2-dimensional memory array is achieved with a 4F2 crosspoint array (where F is the minimum resolvable feature size) where at each of the intersections of perpendicular wiring lines is the memory cell. In order to form a crosspoint memory array for resistive memory (examples: phase change memory (PCM) or RRAM) the memory element is comprised of a memory cell and an access device. It is advantageous to fabricate the memory array with a minimal number of masking steps and processing steps, however, an adequate number of processing steps of certain types is required for forming a reliable memory cell. A single patterning using Reactive Ion Etching (RIE) of the memory element and the access device would minimize the number of masking layers and processing steps, however, there are cases in which it is impossible to pattern the memory element using RIE without also damaging or modifying the memory element during the RIE.
Resistance drift of the amorphous region of the phase change material is a reliability concern, especially for MLC PCM. One method to mitigate this resistance drift is to include an Rs tuned liner in the PCM cell so that the read current path utilizes this liner and bypasses the amorphous region of the phase change material. The drawback of combining these two features is that the lowest achievable resistance is increased by the liner and the resistance of the thin film liner is difficult to control due to the highly non-linear resistivity vs. thickness.